The Intel 8087, released in 1980 as the x86 family's first floating-point coprocessor, used a purpose-built 80-bit adder at the heart of its arithmetic pipeline — this week's Hackaday die-level teardown walks the exact silicon: a carry-lookahead adder shared across normalization, alignment, and final result computation, arranged to keep transistor count within the era's 40,000-transistor 3 µm NMOS process budget. It's a case study in what "one instruction, many microcycles" architecture looks like at the die level.
In brief — 2026-06-23 · A Hackaday die-level writeup walks the adder at the core of Intel's 8087 FPU, exposing microcode-driven pipeline reuse that packed 80-bit floating-point into a 40,000-transistor budget.
What happened: the Hackaday 8087 writeup
Ken Shirriff's die-level analysis of the Intel 8087, republished this week on Hackaday, dissects the 80-bit adder that sat at the arithmetic center of Intel's first floating-point coprocessor. The article follows every stage from operand fetch out of the register stack, through mantissa alignment, into the shared adder, and back out to normalization — using annotated die photos to show which physical transistors implement each microarchitectural step.
The finding that stands out is architectural reuse: the same 80-bit adder does mantissa alignment, mantissa addition, and post-adder normalization. In modern FPU designs those are three separate pipelined units. In the 8087, where every transistor is expensive (the whole chip is only ~45,000 devices in a 3 µm NMOS process), the adder is time-multiplexed across those roles by a microcode sequencer. One instruction — say, FADD — expands into many microcycles, each of which routes the adder differently.
That's why the 8087 famously took many clock cycles to complete a single floating-point operation. FADD in the 8087 datasheet lists 70–100 clocks. A modern x86 FPU pipelines an FADD in a couple of clocks. The 8087 traded latency for silicon budget — an entirely rational choice in 1980.
Why it matters: the lineage from 8087 to today's FPUs
The 8087 introduced the x87 instruction set, which every x86 CPU shipped for the next 25 years still implemented (often microcoded on top of newer SSE/AVX hardware, but architecturally exposed). Its 80-bit extended-precision internal format — 64 bits of mantissa, 15 bits of exponent, one bit of sign — is why C's long double on x86 is 80 bits, why floating-point rounding on x86 has some quirks that RISC architectures don't share, and why the FPU's stack-based register model bothers compiler writers to this day.
Every hackable "how do FPUs really work?" tutorial written since 1980 traces back to the 8087. Homebrew CPUs on FPGAs almost always ship a soft-FPU inspired by the 8087's adder-reuse pattern, because it's the smallest silicon budget that gets you real floating-point. If you're building a 6502 add-on FPU on a Raspberry Pi platform or teaching an intro microarchitecture class, the 8087 remains the reference.
The source
Hackaday has been publishing Shirriff's die-level chip writeups for years; this one is the deepest 8087 walk to date. The archived die photos and annotations are freely available.
Historical context: why Intel built the 8087 in 1980
The 8086, launched in 1978, had no floating-point instructions. Software emulation of floating-point on the 8086 ran 30–100× slower than integer arithmetic. Scientific, CAD, and financial workloads — the segments Intel wanted to sell x86 chips into — were dead-in-the-water without a hardware FPU. The 8087 was Intel's answer: an optional companion chip, socketed alongside the 8086, that snooped the same bus and executed floating-point instructions in parallel with integer instructions.
The parallel-execution model is elegant. When the 8086 encountered an ESC (escape) instruction — the mechanism for offloading to the 8087 — it prefetched operands and waited on a WAIT instruction while the 8087 crunched. Both chips saw the same instruction stream; the 8087 filtered for the ESC-prefixed opcodes it cared about. This is a beautifully cheap way to build a coprocessor.
Table: what the 8087 shipped vs modern x86 FPUs
| Aspect | Intel 8087 (1980) | Modern x86 (2026) |
|---|---|---|
| Process | 3 µm NMOS | 3 nm / 5 nm FinFET |
| Transistors | ~45,000 | Billions |
| Extended precision | 80-bit | 80-bit (still exposed via x87), 64/32-bit for SSE/AVX |
| FADD latency | 70–100 clocks | 3–5 clocks |
| Pipelined? | No — shared adder | Fully pipelined vector ALU |
| Package | 40-pin DIP | Integrated on-die |
| Cost (1980 / 2026 $) | $500 / $1,900 | Included |
Numbers rounded from the 8087 datasheet and modern Intel/AMD architecture reference manuals.
Why makers still learn from the 8087
If you're building a small computer today — a homebrew retro machine, an FPGA soft-CPU, a Raspberry Pi-hosted educational core — the 8087's design lessons still apply. Silicon (or LUTs) are limited. Sharing a single adder across microcycles is often the correct choice. Microcode is a superpower for keeping the ISA rich while the datapath stays cheap. All of that is 8087 practice.
Some of the best hobbyist projects riffing on this today are hosted on a Raspberry Pi 4 Model B 8GB — enough compute to run a modern FPGA toolchain and an emulator side-by-side. The Vilros Raspberry Pi Zero W Starter Kit is the go-to for lower-power educational builds; the 8BitDo Sn30 Pro controller is a common companion when the project ends up being a computer + retro-console hybrid.
Common misconceptions about the 8087
"The 8087 was slow because it was NMOS." Not quite. The process was constrained, but the adder-reuse pattern was the primary latency driver. A 3 µm CMOS 8087 with the same architecture would have been faster on absolute clocks but still microcycle-heavy per FADD.
"The 80-bit format was Intel's idea alone." It was influenced heavily by William Kahan (the same computer scientist who drove IEEE 754 to a finished spec). The 8087 shipped before IEEE 754 was final and is often credited with helping shape the standard's final form.
"x87 is dead." Architecturally, no. AMD64 (x86-64) formally deprecates x87 in favor of SSE/AVX, and every modern compiler defaults to SSE for floating-point. But the x87 instructions are still decoded, x87 state is still saved/restored on context switch, and long double on Linux x86-64 is still x87 80-bit. It's a low-priority-but-alive part of every modern x86.
Practical takeaways for hobbyist chip archaeology
If you're new to reading die photos and want to walk from the 8087 outward, the pattern to follow is:
- Start with the datasheet's block diagram — the 8087 datasheet's Figure 3 is the roadmap.
- Overlay the block diagram on Shirriff's annotated die photo. Find the register stack (top of chip), the microcode ROM (lower left), the adder (center), and the exponent/normalize units (right).
- Trace a single instruction — FADD is the classic — through the block diagram, then re-locate each step on the die.
- Read the microcode-cycle table (also in the datasheet) and count microcycles per instruction. That gives you the "why is it so slow?" answer.
Total time: an afternoon. The reward: a genuine intuition for how 1980-era integrated FPUs worked, and by extension, why the pipeline decisions of every FPU since have looked the way they do.
FAQ
The FAQ block below appears in the article's structured metadata for Google's rich-results treatment.
Common misconceptions readers ask us about
"Was the 8087 the first FPU?" No. Motorola 68881, Intel iAPX 432 GDP, DEC PDP-11 optional FPUs, and various IBM System/360 arithmetic units predated it. The 8087 was the first x86 FPU and the first mass-market FPU on a personal computer.
"Why 80 bits?" Kahan's argument was that intermediate precision needed to exceed working precision so rounding errors wouldn't compound. 32-bit floats need 64-bit intermediates; 64-bit floats need 80-bit intermediates. Modern IEEE 754 keeps that logic in the "extended precision" tier.
"Did the 8087 use IEEE 754?" Not the final ratified standard — 754 came out in 1985, the 8087 in 1980. But it implemented the draft close enough that it shaped the final spec. Later x86 FPUs are fully 754-compliant.
"Is it worth studying the 8087 today?" Yes if you build compilers, CPUs, or emulators. Not really if you're an application-level developer.
When 8087-era design lessons still apply
- FPGA soft-CPUs. Fitting a decent FPU into a small FPGA — an ICE40, an ECP5, an early Artix — means adopting the 8087's shared-adder pattern. There isn't LUT budget for a fully-pipelined vector unit.
- Microcontroller floating-point emulation. The
soft_floatlibrary on RISC-V microcontrollers borrows from the same playbook. - Emulator design. Writing a 68000 or i386 emulator that models the FPU correctly requires understanding how microcycles route through a shared adder.
When they don't
- Modern OoO x86 or AArch64 microarchitecture is a different world. Registers rename, ops are speculative, adders are duplicated and pipelined. The 8087 pattern is historical, not current.
- GPUs are shaped by parallel-lane math, not by shared-adder microcycles. Learning 8087 doesn't teach you GPU design.
Comparison: 8087 vs Motorola 68881 (the two 1980s FPU coprocessors)
| Aspect | Intel 8087 (1980) | Motorola 68881 (1984) |
|---|---|---|
| Register model | 8-register stack | 8-register direct-access |
| Extended precision | 80-bit | 80-bit |
| Transistors | ~45,000 | ~155,000 |
| Interface | Synchronous escape opcodes | Coprocessor bus |
| FADD latency | 70–100 clocks | 45–60 clocks |
| Process | 3 µm NMOS | 2 µm CMOS |
| Legacy | Every x86 CPU still exposes x87 | 68881 died with 68k |
The Motorola design's direct-register model was cleaner for compilers and later became the ARM VFP model, one reason ARM is nicer to write assembly for.
Real-world example: reading the 8087 today
If you want to actually do the die-reading exercise yourself:
- Grab the Intel 8087 datasheet PDF (Bitsavers has it).
- Load Ken Shirriff's annotated die photo from his blog.
- Open the Wikipedia page on IEEE 754 for the encoding rules.
- Sit down for a Saturday afternoon and trace FADD.
A Raspberry Pi 4 Model B 8GB running a modern browser handles the PDFs, high-res die images, and a scratch FPGA simulator in parallel. That's the 2026 hobbyist workstation.
What a 2026 hobbyist actually builds after reading the 8087 writeup
The most common builds we see after readers dive into 8087 archaeology:
- A soft-CPU on an FPGA dev board. Lattice ECP5-based boards run about $80 and fit a small Zilog Z80 or 6502 clone plus a 16-bit FPU that borrows the shared-adder trick.
- A retro-PC restoration. A working 486DX2/66 build with a genuine 80487 socketed alongside the 486SX (functionally an 80487 chip masquerading as an FPU-less CPU with a slot for the "coprocessor" — a great piece of packaging history).
- A homebrew emulator. Emulators for classic Macs (Motorola 68881 FPU), classic PCs (8087 / 80287 / 80387), or the Nintendo 64 (which has a proper 64-bit FPU) all rely on knowing the microcycle patterns of the underlying hardware.
- An educational writeup for a class. The 8087 remains the reference case study in undergrad computer architecture classes.
Adjacent hardware to explore next
- Motorola 68881 (1984) — the FPU that shipped alongside the 68020, cleaner register model, shorter latencies.
- Weitek 1167 (1985) — a "coprocessor" that competed with the 8087/287 in the workstation market. Different design philosophy: pipelined, faster, but less compatible.
- RISC FPU designs in the SPARC and MIPS families — where the 8087's stack model gets discarded in favor of registers.
- Modern SIMD FPUs in AVX-512 and ARM SVE, where the compute pattern is vector-wide and the shared-adder era is long gone.
Related guides
- Watching a Z80 Live From a Raspberry Pi RP2350
- Build a RetroPie Arcade on a Raspberry Pi 4 8GB in 2026
- Raspberry Pi 4 8GB as a Local LLM Box: What Models Actually Run?
- Build a Pocket RetroPie Handheld on a Raspberry Pi Zero W (2026 BOM)
