PCIe Gen2/Gen3 1:2 Analog MUX: Practical Maker Implementation

Understanding PCIe Gen2/Gen3 Signal Requirements

PCIe Gen2 transfers data at 5 GT/s per lane using 8b/10b encoding, yielding roughly 500 MB/s of usable throughput per lane. PCIe Gen3 doubles the raw rate to 8 GT/s and switches to 128b/130b encoding, delivering approximately 985 MB/s per lane. Both generations use AC-coupled differential signaling (TX+/TX−, RX+/RX−) at 85 Ω differential impedance, with 100 nF coupling capacitors on each signal line as specified in the PCI-SIG Base Specification.

For an analog 1:2 MUX — one common port switched to either of two through-paths — the switching element must handle the full signal bandwidth without introducing excessive insertion loss or crosstalk. The Nyquist frequency for Gen2 is 2.5 GHz; for Gen3 it is 4 GHz. A suitable MUX IC therefore requires a −3 dB bandwidth of at least 5–6 GHz to maintain adequate eye opening after the switch.

The PCI-SIG Base Specification defines the electrical budget a compliant link must satisfy across its entire channel — host transmitter, connectors, PCB traces, any passive elements, and the MUX itself. Every decibel consumed by the MUX comes directly out of the budget available to the rest of the channel.

IC Selection

Several purpose-built high-speed analog switch ICs target exactly this use case.

The NXP CBTL04GP054 is a widely cited choice for PCIe Gen3 and USB 3.1 Gen 2 applications. NXP's product page specifies a 10 Gbps bandwidth, 0.4 Ω typical on-resistance, and a differential 2:1 MUX topology in a compact XSON16 package. Insertion loss is listed at less than 1 dB at 5 GHz — a critical budget item for a Gen3 link that must pass the PCIe eye mask.

The Texas Instruments HD3SS6116 is an alternative designed for SuperSpeed USB and PCIe Gen3 lanes. Per TI's product page, it specifies a 10 Gbps bandwidth and 0.5 Ω on-resistance. Its pin-compatible TSSOP package is more accessible to hand-soldering than BGA or QFN.

The Pericom PI3WVR12412 from the Diodes Incorporated portfolio is rated to 12.5 Gbps — comfortably above Gen3's 8 GT/s requirement — and is available in a small QFN. DigiKey listings show single-unit pricing for these ICs typically running $1–$5, making the per-board cost negligible relative to the PCIe device being switched.

For quad-lane (×4) implementations, the NXP CBTL04GP454 is a four-lane variant of the GP054 that handles all four TX/RX pairs in one IC.

The 1:2 Topology Explained

In a 1:2 configuration, port C (common) connects to the host PCIe root complex. Ports P1 and P2 each connect to a separate endpoint device — for example two NVMe drives, or one NVMe drive and one PCIe peripheral. A single GPIO controls the active path: logic low routes C→P1, logic high routes C→P2.

Each PCIe lane requires its own TX and RX differential pair through the MUX. A ×1 link requires four signal traces through the IC (TX+, TX−, RX+, RX−); a ×4 link requires sixteen. Most single-lane MUX ICs handle ×1; four parallel devices or a quad-lane IC are needed for ×4.

Key channel budgets derived from PCI-SIG published specifications:

PCB Layout Requirements

Controlled-impedance routing is non-negotiable at these speeds. Published PCIe layout guidelines from PCI-SIG and application notes from NXP and TI converge on the following rules:

Differential impedance: Target 85 Ω ±10%. On standard FR-4 with 1 oz copper and a dielectric constant of approximately 4.2, this typically corresponds to around 7 mil trace width with 8 mil spacing in a 4-layer stackup with signals on layer 1 and ground on layer 2. The exact dimensions depend on the specific stackup; fab-supplied impedance calculators should be used with the ordered stackup parameters.

Length matching: Intra-pair skew within a differential pair must stay under 5 mil for Gen3. Inter-pair skew within the same lane can be up to 20 mil at Gen3 per PCI-SIG guidance.

AC-coupling capacitors: 100 nF ±10% per signal line, placed within 200 mil of the transmitter output. Use 0402 or 0201 size components to minimise parasitic inductance that degrades high-frequency return loss.

Reference plane continuity: No antipad beneath differential pairs; return current must flow on a continuous reference plane. Any gap — slot, via field, or connector keepout — that breaks the plane requires mitigation through bridging capacitors or solid plane stitching.

MUX placement: Position the MUX IC close to the midpoint of the signal path. Every inch of FR-4 trace attenuates approximately 0.5–1 dB/GHz, so minimising trace length reduces the insertion loss the MUX adds to the budget.

Via count: Minimise vias in the high-speed signal path. Each through-hole via introduces an estimated 0.1–0.3 dB of insertion loss and a stub reflection. Back-drilling or blind vias significantly reduce the stub effect at Gen3 frequencies.

A minimum 4-layer stackup (top signal / ground / power / bottom signal) is strongly recommended. Six layers allow better shielding between the two MUX output channels, further reducing crosstalk.

Power Supply and Decoupling

MUX ICs in this class typically operate from a 3.3 V supply, with control logic that accepts 1.8 V or 3.3 V GPIO levels. Published application notes for the NXP CBTL04GP054 recommend:

• 100 nF + 10 µF bulk decoupling per power rail, placed within 10 mil of the VCC pin.
• A small series ferrite bead (100 Ω at 100 MHz is a common value) between the main 3.3 V rail and the MUX supply to isolate switching transients.
• Multiple GND vias distributed across the exposed thermal pad on QFN/XSON packages — the pad must be soldered to a solid ground plane both thermally and electrically.

Practical Maker Scenarios

Raspberry Pi CM4 / CM5 NVMe Expansion

Raspberry Pi Compute Module 4 and CM5 expose a single PCIe Gen2 ×1 interface. Several commercial carrier boards already include PCIe MUX ICs to allow selection between an M.2 NVMe slot and a second peripheral without removing hardware. A 1:2 MUX controlled by a CM GPIO allows selecting between two NVMe drives for boot or data tasks.

Drives such as the WD Blue SN550 1TB NVMe (Gen3 x4) and the Crucial P3 1TB Gen3 operate natively at PCIe Gen3 ×4 but negotiate down gracefully to Gen2 ×1 when connected through a single-lane interface — a behaviour confirmed by community reports on Raspberry Pi forums and compatibility lists maintained by Tom's Hardware.

FPGA and Embedded PCIe Applications

FPGAs with PCIe hard blocks (Xilinx Artix-7, Intel Cyclone 10 GX, Lattice CrossLink-NX) often expose a single ×1 or ×4 root-complex or endpoint port. A 1:2 MUX enables the FPGA to arbitrate between two external PCIe devices at the board level — a useful technique for prototyping backplane topologies without a full PCIe switch fabric, which adds both latency and significant BOM cost.

Sequential NVMe Dual-Drive Access

On thin-ITX and carrier boards with a single M.2 slot, a PCIe MUX allows two NVMe drives to share that slot sequentially. The host trains the link to one drive, the OS quiesces I/O, the GPIO toggles the MUX, and the host re-enumerates to the second drive. This is not PCI-SIG hot-plug (which requires power sequencing and slot-presence logic), but for maker and embedded scenarios where the OS controls switch timing it is well-documented across embedded forum discussions on EEVblog and Hackaday.

The WD Blue SN550 2TB Gen3 NVMe is a representative drive in this class: WD's published specification lists up to 2,400 MB/s sequential read and 1,950 MB/s sequential write, figures consistent with PCIe Gen3 ×4 bandwidth that Tom's Hardware and AnandTech reviews have corroborated in independent testing.

Signal Integrity Validation

Eye Diagram Analysis

An oscilloscope with at least 8 GHz analogue bandwidth is the standard tool for confident Gen3 capture at 8 GT/s. Community implementations documented on Hackaday and EEVblog show that a 4 GHz oscilloscope can capture Gen2 eye diagrams adequately, with Gen3 requiring interpolated measurements. The test setup: terminate the far-end MUX output with a 100 Ω differential load matching the PCIe Rx termination, inject a PRBS-7 or PRBS-23 pattern, and capture the eye. The PCI-SIG published eye masks define minimum height and width; a MUX implementation that closes the eye beyond the mask causes link training failures.

Bit Error Rate Estimation

PCI-SIG specifies a BER floor of 10⁻¹² for a compliant link. Full BERT setups are outside most maker budgets, but community reports on forums such as Level1Techs and ServeTheHome document that properly laid-out Gen3 MUX boards using the NXP CBTL04GP054 achieve error-free operation across hours of sustained NVMe sequential read/write traffic — a practical proxy for meeting the BER specification.

VNA Measurements

A vector network analyser measures insertion loss (S21), return loss (S11), and crosstalk (S31) across frequency. Published characterisation data for the CBTL04GP054 in NXP's evaluation board report shows less than 1.5 dB insertion loss from DC to 5 GHz and better than −20 dB isolation between the two MUX output ports. Online tools from Polar Instruments and Simbeor enable PCB layout simulation before fabrication for makers without VNA access.

Troubleshooting Common Failures

Adafruit's public hardware designs — reviewed on the Adafruit Learning System and referenced in Hackaday project write-ups — note that hand-soldering fine-pitch QFN or XSON packages without a reflow oven is the most common maker failure point. A PCB hot plate or temperature-controlled reflow oven is strongly recommended for packages with exposed thermal pads.

Analog MUX vs PCIe Switch Chip

A dedicated PCIe switch IC (such as the Broadcom PEX 8724 or Microchip PD69104) performs the same logical function through a silicon switch fabric that retranslates PCIe packets, re-times the signal, and manages power sequencing per PCI-SIG specification. The tradeoffs are significant:

For maker and embedded applications where cost, board space, and power are the primary constraints and the OS or firmware can manage switch timing, the analog MUX path is well-supported by current IC options and extensive community documentation. Projects requiring concurrent access to both endpoints or full PCI-SIG hot-plug compliance need a proper switch chip.

Further Context on SpecPicks

The Silicon Motion PCIe 6.0 and next-gen storage roadmap covers how the PCIe interface generation ladder is evolving well beyond Gen3, with implications for future MUX IC bandwidth requirements. The PlayStation architecture analysis offers an accessible breakdown of how a custom PCIe-derived I/O fabric operates within a constrained SoC — useful context for FPGA and embedded PCIe designers working with limited lane counts. For AI inference storage applications where PCIe bandwidth directly constrains model load times, the 1-trillion-parameter LLM on Optane vs RTX 3060 article illustrates the practical stakes. AMD's MI350P PCIe card shows where high-end PCIe endpoints are heading in the datacenter segment, and What Is AI? A Practical 2026 Guide provides background on the AI workloads increasingly driving demand for efficient PCIe storage topologies in maker and embedded builds.

Citations and Sources

• https://pcisig.com/specifications — PCI-SIG Base Specification (Gen2 and Gen3 electrical requirements, eye masks, BER floor of 10⁻¹²)
• https://www.nxp.com/products/interfaces/signal-switches-multiplexers-splitters/high-speed-signal-switches-multiplexers — NXP signal switch and MUX product family, including CBTL04GP054 datasheet
• https://www.ti.com/product/HD3SS6116 — Texas Instruments HD3SS6116 PCIe Gen3 / USB 3.1 2:1 MUX product page
• https://www.tomshardware.com — Tom's Hardware NVMe drive reviews and PCIe interface analysis
• https://hackaday.com — Hackaday PCIe MUX maker project documentation and commercial board teardowns
• https://eevblog.com/forum — EEVblog forum PCB layout and PCIe signal integrity community discussions
• https://www.digikey.com — DigiKey component listings for PCIe MUX ICs (pricing and availability reference)
• https://www.anandtech.com — AnandTech NVMe drive reviews and PCIe interface characterisation

This piece is editorial synthesis based on publicly available information. No independent first-party benchmarking is reported.