STEPLA-1 8-Bit Hardwired CPU: 74-Series Logic Explained

What Is the STEPLA-1? A Hardwired 8-Bit CPU From Discrete Logic

The STEPLA-1 is an 8-bit CPU design built entirely from discrete 74-series (7400 family) logic integrated circuits — a category of standardized logic ICs in continuous production since the 1960s. Unlike commercial processors from Intel, AMD, or Arm, which pack billions of transistors onto a monolithic die using 5nm–7nm process nodes, the STEPLA-1 achieves computational function by wiring together individual chips that each implement a basic Boolean operation: AND, OR, NAND, NOR, XOR, flip-flops, and registers.

This approach is called hardwired or random logic CPU design. The processor's instruction-decode and control signals are determined by the physical interconnection of gates, not by a stored microprogram. It contrasts with microcoded architectures, in which a ROM table maps each instruction opcode to a sequence of micro-operations — the approach used by the Intel 8086 and carried forward in various forms into modern x86-64 designs.

The STEPLA-1 sits in the maker/educational tradition alongside Ben Eater's widely documented SAP-1 ("Simple As Possible") 8-bit breadboard computer, which uses the same 74LS and 74HC families. That project, documented at eater.net/8bit, has become a primary reference for anyone building a CPU from first principles. The STEPLA-1 extends the concept toward a more complete ISA and PCB-ready implementation — a natural next step for builders who've outgrown the breadboard.

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The 74-Series Logic Family: Still Relevant in 2026

The 7400 family comprises hundreds of standardized logic functions across multiple subfamilies. The modern CMOS variant — 74HC (High-speed CMOS) — operates on 2V–6V supplies, draws microamp-range quiescent current per package, and remains in active production from Texas Instruments, Nexperia, Toshiba, and onsemi as of 2026. Per the Texas Instruments Logic Guide (SDYU001), the HC subfamily offers typical propagation delays of 7–9 ns at 5V, which sets the ceiling on achievable clock frequency in any discrete design.

Key ICs that appear in nearly every 74HC CPU design:

A complete 8-bit CPU from this family requires approximately 30–60 ICs depending on ISA complexity. More capable instruction sets — conditional branches, a hardware stack, interrupt support — push the package count toward the upper end. Simpler "fetch, decode, execute" designs with four or five instructions can be realized with fewer chips.

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Hardwired vs. Microcoded: The Core Architectural Trade-Off

In a microcoded CPU, each machine instruction triggers a microsequencer that steps through micro-operations stored in a ROM or PLA. This makes ISA changes relatively cheap (edit the ROM contents, not the board layout) and lets complex instructions decompose into many simple steps — the rationale behind the CISC designs of the 1970s and 1980s.

In a hardwired CPU, the control unit is a combinational or sequential logic network that directly asserts control signals for each instruction during each clock phase. The trade-offs, documented in Hennessy and Patterson's Computer Organization and Design, break down as follows:

For maker and educational use, the hardwired approach wins on observability: every control signal is a physical wire that can be intercepted with a logic analyzer or oscilloscope. The fetch-decode-execute cycle is not an abstraction — it is a sequence of voltage transitions that a builder can watch in real time.

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Signal Integrity and PCB Design Considerations

Moving a 74HC CPU from breadboard prototype to a two- or four-layer PCB introduces signal integrity challenges that breadboards can mask. Per the Texas Instruments application note PCB Design Guidelines for HC/HCT Logic (referenced in SDYU001), the principal concerns at 74HC switching speeds are:

Decoupling capacitors are non-negotiable. Every VCC pin should have a 100 nF ceramic capacitor within 5mm of the package. Insufficient decoupling produces supply rail noise that causes spurious triggering in flip-flop stages — one of the most common causes of intermittent failures in first-time TTL builds.

Fanout limits bound bus design. Each 74HC output can drive 10 unit loads (74HC inputs) at 5V per TI specifications. Any bus node with more than approximately 8 loads requires a dedicated bus driver such as the 74HC245 or 74HC541. Overlooking fanout is the second most common debugging pitfall reported in community build threads on Hackaday.

Clock distribution skew accumulates across registered stages. A star-topology clock distribution, where a single-source driver fans out symmetrically to each register stage, keeps setup and hold margins predictable. Daisy-chained clock routing introduces progressive skew that becomes a timing problem at higher clock speeds.

Transmission line effects become relevant above roughly 10 MHz for traces longer than 5 cm. At the 1–5 MHz operating points typical of educational 74HC designs, this is rarely a limiting factor, though a solid ground plane remains essential for any digital board regardless of speed.

The Gigatron TTL microcomputer project — a complete 8-bit TTL computer that runs commercial game software — documents practical mitigations for all of these issues in its open-source design files, providing a useful reference for STEPLA-1 builders dealing with similar challenges.

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Power Consumption: A Genuine Advantage of 74HC Logic

One underappreciated characteristic of 74HC-based CPU designs is their power envelope. Per TI's HC family datasheet, quiescent supply current (I_CC) is typically 80 µA per package at 5V. For a 50-IC design running at 1–2 MHz:

Quiescent power ≈ 50 packages × 80 µA × 5V ≈ 20 mW

Dynamic switching power scales with clock frequency and capacitive load, but at 1–5 MHz a complete CPU system including SRAM and EEPROM typically stays under 500 mW total. For context, TechPowerUp's measured TDP data places the AMD Radeon RX 7900 XTX at 330W under full GPU load. The comparison illustrates the purpose-fit difference: discrete logic CPUs are not throughput engines — they are architecture demonstration and control systems where watt-level power budgets are a genuine asset.

This power profile makes 74HC CPU designs suitable for battery-powered educational kits, remote data-logging controllers, or retro-computing demonstrations where exposition of CPU architecture, not throughput, is the primary goal.

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Clock Speed and Throughput: Setting Accurate Expectations

The maximum clock frequency of a 74HC CPU is bounded by the longest combinational path through its control logic — the critical path. With 74HC propagation delays of 7–9 ns per gate stage and a typical critical path of 3–5 gate stages:

Theoretical f_max ≈ 1 / (5 × 9 ns) ≈ 22 MHz

In practice, PCB parasitics, fanout loading, and setup/hold timing margins reduce achievable frequencies significantly. Community builders of 74HC SAP-1 variants consistently report stable operation in the 1–10 MHz range, per discussions on eater.net/8bit and related forums. A conservative 1–2 MHz operating point provides comfortable timing margin on most layouts.

At 1 MHz executing simple 2-cycle instructions, an 8-bit hardwired CPU processes on the order of 500,000 instructions per second. That ceiling is adequate for:

• Sensor polling and state-machine control in maker projects
• Educational demonstrations of pipelining, interrupts, and memory-mapped I/O
• Small games, BASIC interpreters, and terminal I/O, exactly as 1970s microcomputers did

It is not intended to compete with modern compute workloads. For scale, AMD's published performance data for the Ryzen 5 7600X places it at approximately 20 billion instructions per second under SPEC CPU 2017 workloads. The contrast is instructive rather than competitive: these are instruments built for different jobs, in the same way that a mechanical watch is not competing with an atomic clock.

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Bill of Materials and Sourcing in 2026

74HC parts remain in full production with plentiful stock at Digi-Key, Mouser, and LCSC as of 2026. LCSC — the component arm of PCB fabricator JLCPCB — has become the dominant low-cost source in the hobbyist community, with stock exceeding 100,000 units on high-velocity parts like the 74HC245 and 74HC574. A representative BOM for a complete 8-bit hardwired CPU:

Total estimated BOM cost: $50–$120 USD for a PCB-based 8-bit CPU system, excluding verification equipment. Pricing is based on 2026 distributor listings; component costs at LCSC in particular have declined year-over-year as HC production has been consolidated onto modern CMOS processes.

For the EEPROM in particular, the AT28C256 and AT28C64 variants from Microchip (formerly Atmel) remain the community standard because they support parallel programming with simple DIY programmer circuits — no high-voltage programming rail required.

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Why Build One in 2026?

With FPGAs available for $10–$50 (Lattice iCE40, ECP5 families), microcontrollers starting at $0.50 (RP2040, STM32G0), and cycle-accurate simulators like Logisim-Evolution freely available, the pragmatic question arises: why build a 74HC CPU from ICs in 2026?

The answer documented across builder communities on Hackaday and eater.net is physical legibility. Every signal in a TTL/CMOS discrete CPU is a wire that can be physically intercepted with a probe. No toolchain, firmware blob, or vendor HAL stands between the builder and the logic. For learners building genuine intuition about CPU architecture, that observability is pedagogically irreplaceable — an FPGA softcore is correct and fast, but it is also opaque.

Secondary motivations documented by the community include:

• Historical fidelity: Understanding at the gate level how the MOS 6502, Zilog Z80, and Intel 8085 were actually designed
• Constrained design challenges: What is the minimum gate count for a Turing-complete ISA? How few chips can implement a useful interrupt controller?
• PCB craftsmanship: Multi-layer routing of a 50+ IC design builds layout skills directly applicable to more complex commercial-grade projects
• Documentation as artifact: A completed 74HC CPU on a PCB is a tangible, inspectable record of architectural understanding that no simulation produces

The Gigatron TTL project — which shipped as a commercial kit and runs Tetris and a BASIC interpreter — demonstrates that the class of design is not merely theoretical. A fully functional, useful 8-bit computer can be built from these parts by a motivated maker with intermediate electronics skills.

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Frequently Asked Questions

Can a 74HC hardwired CPU run real software?

Yes — assembly programs, BASIC interpreters, and control applications are all feasible at this architecture level. Community projects in the same 74HC tradition have run complete small operating systems and games. Modern Linux and web browsers are far out of reach, but the full software ecosystem of late-1970s and early-1980s microcomputers is achievable.

Is the STEPLA-1 open-source?

The STEPLA-1's licensing and file availability should be verified against its official project repository. Many comparable TTL CPU projects — Ben Eater's SAP-1, the Gigatron TTL computer — are MIT or Creative Commons licensed, making schematics, PCB Gerbers, and assembler source freely available to builders.

How does a 74HC discrete CPU compare to an FPGA softcore?

An FPGA softcore (RISC-V, 6502 clone) runs at 50–200 MHz and costs $5–$50 for the programmable device. A discrete 74HC CPU runs at 1–10 MHz and costs $50–$120 in components. The FPGA wins on performance and recurring cost; the discrete build wins on physical legibility — every gate, every bus, every control signal is directly probeable.

What debug tools are needed for a 74HC CPU build?

A logic analyzer is the most important instrument — 8-channel USB units are available from $10 to $150. An oscilloscope helps verify clock edge quality and timing margins. Community build reports consistently emphasize that a structured debugging methodology, starting from the clock signal and working outward bus by bus, matters more than any specific instrument.

What is the difference between 74LS and 74HC logic?

74LS (Low-power Schottky) is a bipolar TTL subfamily from the 1970s — functional but largely superseded and drawing more quiescent current. 74HC (High-speed CMOS) offers lower power, a wider supply range (2V–6V), and inputs compatible with 3.3V systems. Per Texas Instruments' Logic Guide, 74HC or 74HCT is the recommended choice for any new discrete logic design in 2026.

How long does building a 74HC CPU typically take?

Community build logs for comparable projects — Ben Eater's 8-bit breadboard computer and the Gigatron TTL microcomputer — report 40 to 200 hours of design, assembly, and debugging time depending on experience level. A PCB-based build starting from a tested, published schematic significantly compresses the total compared to a breadboard-first approach.

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Citations and Sources

• https://eater.net/8bit — Ben Eater's 8-bit breadboard computer project; primary community reference for SAP-1 class CPU builds using 74-series logic
• https://www.ti.com/lit/sg/sdyu001ab/sdyu001ab.pdf — Texas Instruments Logic Guide: 74HC/HCT family propagation delays, fanout, decoupling, and PCB design guidelines
• https://gigatron.io — Gigatron TTL microcomputer project; open-source 8-bit TTL CPU and kit demonstrating full software capability from discrete logic
• https://hackaday.com — Hackaday community coverage of 74-series and TTL CPU maker projects, including builder reports and signal integrity discussions
• https://www.amd.com/en/products/processors/desktops/ryzen/7000-series/amd-ryzen-5-7600x.html — AMD Ryzen 5 7600X product page, cited for modern CPU performance context
• https://www.techpowerup.com/gpu-specs/radeon-rx-7900-xtx.c3804 — TechPowerUp Radeon RX 7900 XTX specifications, cited for measured TDP power reference

This piece is editorial synthesis based on publicly available information. No independent first-party benchmarking is reported.